The most comprehensive PCB fabrication capability reference we publish. Over 120 individually verified parameters across 13 categories — layer stackup, materials, drilling, trace geometry, surface finish, impedance, HDI, signal integrity, environmental reliability and more. Searchable, filterable, three-tier graded.
Every specification our fab line is qualified against — searchable and filterable in real time. Use the search bar or category pills to find exactly the parameter you need.
| Category | Parameter | Standard | Advanced | High-Precision |
|---|---|---|---|---|
| Layers | Layer Count | 1 – 16 layers | 18 – 30 layers | 32 – 44 layers |
| Layers | Max. Board Dimensions (2L FR4) | 610 × 1200 mm | — | — |
| Layers | Max. Board Dimensions (Multilayer) | 580 × 1100 mm | 560 × 1050 mm | 520 × 900 mm |
| Layers | Min. Board Size | 3 × 3 mm | — | — |
| Layers | Board Thickness Range | 0.2 – 6.4 mm | — | — |
| Layers | Thickness Tolerance (T ≥ 1.0 mm) | ±10% | ±8% | ±5% |
| Layers | Thickness Tolerance (T < 1.0 mm) | ±0.10 mm | ±0.08 mm | ±0.05 mm |
| Layers | Thickness Tolerance (T = 1.6 mm ML) | ±0.18 mm | ±0.13 mm | ±0.10 mm |
| Layers | Thickness Tolerance (T = 2.5 mm ML) | ±0.23 mm | ±0.18 mm | ±0.13 mm |
| Layers | Min. Circular PCB Panel Size | ≥ 20 × 20 mm | — | — |
| Layers | Warp and Twist | ≤ 0.75% | ≤ 0.50% | ≤ 0.35% |
| Materials | Standard FR-4 (Tg 135°C) | Available | — | — |
| Materials | Mid-Tg FR-4 (Tg 150 – 170°C) | Available | — | — |
| Materials | High-Tg FR-4 (Tg 170 – 220°C) | Available (IT158/IT180A) | — | — |
| Materials | Metal-Core MCPCB | Aluminum-core / Copper-core | — | — |
| Materials | RF Laminate — Rogers + FR4 Hybrid | Rogers 4000 series + FR4 mixed | — | — |
| Materials | RF Laminate — Pure Rogers | — | Rogers 4350B / 4003C / RT/duroid | — |
| Materials | PTFE / Teflon Laminate | Available (Dk 2.1 – 2.5) | — | — |
| Materials | CEM-3 (Glass Composite) | Available | — | — |
| Materials | Polyimide (Flex-Rigid Base) | Available | — | — |
| Materials | Halogen-Free / RoHS Compliant | Available on request | — | — |
| Copper | Outer Layer Copper Weight | 0.5 – 3 oz | 4 – 8 oz | 10 – 20 oz |
| Copper | Inner Layer Copper Weight | 0.5 – 2 oz | 3 – 4 oz | 5 – 6 oz |
| Copper | Heavy Copper Max | Up to 20 oz (700 µm) — busbar / high-current designs | ||
| Copper | Standard Default | 1 oz outer / 0.5 oz inner | — | — |
| Copper | Copper Thickness Tolerance | ±10% | ±8% | ±5% |
| Copper | Min. Plated Copper in Barrel | ≥ 20 µm | ≥ 25 µm | ≥ 30 µm |
| Copper | Average Plating Thickness (Through-Hole) | 20 – 25 µm | 25 – 30 µm | 30 – 35 µm |
| Copper | Peel Strength (1 oz Cu) | ≥ 1.05 N/mm (IPC-TM-650) | — | — |
| Drilling | Mechanical Drill Diameter Range | 0.15 – 6.5 mm | — | — |
| Drilling | Min. Mechanical Via Diameter (Finished) | 0.20 mm | 0.15 mm | 0.10 mm |
| Drilling | Min. Laser Via Diameter | 0.10 mm | 0.085 mm | 0.075 mm |
| Drilling | Min. Non-Plated Hole | 0.50 mm | 0.40 mm | 0.30 mm |
| Drilling | Hole Position Tolerance | ±0.075 mm | ±0.05 mm | ±0.025 mm |
| Drilling | PTH Finished Hole Tolerance | ±0.08 mm | ±0.05 mm | ±0.03 mm |
| Drilling | NPTH Finished Hole Tolerance | ±0.05 mm | ±0.03 mm | ±0.02 mm |
| Drilling | Press-Fit Hole Tolerance | ±0.05 mm | ±0.03 mm | ±0.02 mm |
| Drilling | Max. Aspect Ratio (Thickness : Hole) | 8 : 1 | 10 : 1 | 12 : 1 |
| Drilling | Blind / Buried Vias | Fully supported — sequential lamination, up to 44 layers | ||
| Drilling | Backdrill (Controlled-Depth Drill) | 4 – 44L, ≥ 0.8 mm thickness | — | — |
| Drilling | Castellated Holes (Half-Holes) | ≥ 0.5 mm diameter | ≥ 0.4 mm diameter | — |
| Drilling | Plated Slot Min. Width (Multilayer) | 0.35 mm | 0.30 mm | — |
| Drilling | Non-Plated Slot Min. Width | 1.0 mm | 0.8 mm | — |
| Drilling | Blind Slot Min. Width | ≥ 1.0 mm | — | — |
| Drilling | Plated Edges Min. Board Size | ≥ 10 × 10 mm | — | — |
| Trace | Min. Trace / Space (1 oz outer) | 4 / 4 mil (0.10 mm) | 3 / 3 mil (0.075 mm) | 2 / 2 mil (0.05 mm) |
| Trace | Min. Trace / Space (2 oz outer) | 6 / 6 mil (0.15 mm) | 5 / 5 mil (0.125 mm) | 4 / 4 mil (0.10 mm) |
| Trace | Inner Trace / Space (18 µm Cu) | 4 / 4 mil | 3.5 / 3.5 mil | 3 / 3 mil |
| Trace | Inner Trace / Space (35 µm Cu) | 4 / 5 mil | 4 / 4 mil | 3.5 / 3.5 mil |
| Trace | Inner Trace / Space (70 µm Cu) | 6 / 8 mil | 5 / 6 mil | 4 / 5 mil |
| Trace | Inner Trace / Space (105 µm Cu) | 8 / 11 mil | 7 / 9 mil | 6 / 8 mil |
| Trace | Track Width Tolerance | ±20% | ±15% | ±10% |
| Trace | Min. PTH Annular Ring | 0.20 mm | 0.15 mm | 0.10 mm |
| Trace | Min. NPTH Pad Annular Ring | 0.45 mm | 0.35 mm | 0.25 mm |
| Trace | BGA Pad Diameter | ≥ 0.25 mm | ≥ 0.20 mm (ENIG required) | ≥ 0.175 mm |
| Trace | SMD Pad-to-Pad Clearance | 0.15 mm | 0.12 mm | 0.10 mm |
| Trace | Pad-to-Track Clearance | 0.10 mm | 0.08 mm | 0.06 mm |
| Trace | Via Hole-to-Track Clearance | 0.20 mm | 0.15 mm | 0.10 mm |
| Trace | PTH-to-Track Clearance | 0.30 mm | 0.25 mm | 0.20 mm |
| Trace | Trace Coil Min. Width / Space | 0.15 / 0.15 mm | 0.10 / 0.10 mm | — |
| Finish | HASL (Leaded) | Available | — | — |
| Finish | HASL (Lead-Free) | Available | — | — |
| Finish | ENIG (Ni/Au Thickness) | 100 – 150 µin Ni / 3 – 5 µin Au | 200 µin Ni / 5 – 8 µin Au | > 200 µin Ni / > 8 µin Au |
| Finish | ENEPIG | Available (wire-bondable) | — | — |
| Finish | OSP | Available | — | — |
| Finish | Immersion Silver | Available | — | — |
| Finish | Immersion Tin | Available | — | — |
| Finish | Hard Gold (Selective / Edge Connectors) | 5 – 50 µin Au | — | — |
| Finish | Selective Finish (Mixed per Board) | Available — e.g. ENIG + OSP zones | — | — |
| Mask | Soldermask Colors | Green / Black / White / Red / Blue / Yellow / Purple / Matte Green / Matte Black | ||
| Mask | Soldermask Expansion (1:1 Registration) | Available | — | — |
| Mask | Min. Soldermask Bridge (1 oz, Colored) | 0.10 mm (4 mil) | 0.08 mm (3 mil) | 0.05 mm (2 mil) |
| Mask | Min. Soldermask Bridge (2 oz) | 0.20 mm (8 mil) | 0.15 mm (6 mil) | 0.10 mm (4 mil) |
| Mask | Soldermask Opening Tolerance | ≥ 2 mil | ≥ 1.5 mil | ≥ 1 mil |
| Mask | Soldermask Ink Thickness | ≥ 10 µm (per side) | ≥ 15 µm | ≥ 20 µm |
| Mask | Soldermask Dielectric Constant | ~3.8 @ 1 GHz | — | — |
| Mask | Via-in-Pad — Epoxy Filled & Capped | Via diameter 0.15 – 0.55 mm | — | — |
| Mask | Via-in-Pad — Cu Paste Filled & Capped | Available | — | — |
| Mask | Peelable Soldermask | Available | — | — |
| Silk | Silkscreen Colors | White / Black / Yellow / None | ||
| Silk | Min. Line Width | 0.15 mm (6 mil) | 0.10 mm (4 mil) | — |
| Silk | Min. Text Height | 0.8 mm (32 mil) | 0.6 mm (24 mil) | — |
| Silk | Character Width-to-Height Ratio | 1 : 5 | 1 : 6 | — |
| Silk | Pad-to-Silkscreen Clearance | ≥ 0.15 mm | ≥ 0.10 mm | — |
| Impedance | Standard Impedance Tolerance | ±10% | ±7% | ±5% |
| Impedance | Precision Impedance Tolerance | — | ±5% | ±3% |
| Impedance | 50Ω Single-Ended Tolerance | ±5Ω | ±3Ω | ±2Ω |
| Impedance | Supported Layer Count | 4 – 44 layers | — | — |
| Impedance | Reference Structures | Microstrip / Embedded Microstrip / Stripline / Differential Pair / Coplanar | ||
| Impedance | TDR Verification | Coupon-based | 100% panel verified | 100% + report per S/N |
| Panel | V-Score Board Thickness | 0.4 – 3.2 mm | — | — |
| Panel | V-Score Tolerance | ±0.40 mm | ±0.25 mm | ±0.15 mm |
| Panel | V-Score Min. Panel Size | 70 × 70 mm | — | — |
| Panel | V-Score Max. Panel Size | 475 × 475 mm | — | — |
| Panel | Tab-Routing / Mouse-Bite | Standard — 0.5 – 0.8 mm drill, 1.6 or 2 mm spacing | — | — |
| Panel | Min. Tooling Edge Width | 3 mm | — | — |
| Panel | Min. Panelization Spacing | 2 mm | — | — |
| Panel | Routed Outline Tolerance | ±0.20 mm | ±0.15 mm | ±0.10 mm |
| Panel | Max. Production Panel Size | 20 × 24 in (508 × 610 mm) | — | — |
| HDI | HDI Build Type | 1+N+1 | 2+N+2 | Any-Layer (i+N+i, i ≥ 3) |
| HDI | Stacked Microvias | — | 2-level stack | 3+ level stack, filled & capped |
| HDI | Staggered Microvias | Available | — | — |
| HDI | Via-in-Pad (Microvia) | Filled & planarized | — | — |
| HDI | Skip Vias (Layer 1 to Layer 3+) | — | Available | Available |
| HDI | Sequential Lamination Cycles | 1 cycle | 2 – 3 cycles | 4+ cycles |
| HDI | Min. Pad-on-Via (Microvia Capture) | 0.30 mm | 0.25 mm | 0.20 mm |
| HDI | Hatched Ground Plane — Min. Grid Width/Space | 0.25 / 0.25 mm | 0.20 / 0.20 mm | — |
| HDI | Copper-Filled Microvia | — | Available | Available |
| HDI | Buried Resistor / Embedded Passive | — | Available on request | — |
| Signal | FR-4 Dielectric Constant (Dk) @ 1 GHz | ~4.2 – 4.6 (grade dependent) | — | — |
| Signal | FR-4 Loss Tangent (Df) @ 1 GHz | ~0.018 – 0.025 | — | — |
| Signal | Low-Loss FR-4 (Dk / Df) @ 1 GHz | Dk ~3.7 – 4.0 / Df ~0.008 – 0.012 | — | — |
| Signal | Rogers 4350B (Dk / Df) @ 10 GHz | Dk 3.48 / Df 0.0037 | — | — |
| Signal | PTFE Laminate (Dk Range) | Dk 2.1 – 2.5 (formula dependent) | — | — |
| Signal | Prepreg 7628 Dk | ~4.4 @ 1 MHz | — | — |
| Signal | Insertion Loss Characterization | — | Available (test coupon) | Available (per-board report) |
| Environ. | Flammability Rating | UL 94 V-0 | — | — |
| Environ. | Thermal Cycling Range | −55°C to +125°C (IPC-TM-650) | — | — |
| Environ. | Thermal Stress (Solder Float) | 288°C / 10 sec (IPC-TM-650 2.6.8) | — | — |
| Environ. | CAF Resistance | Tested per IPC-TM-650 2.6.25 | — | — |
| Environ. | Moisture Sensitivity Level (MSL) | MSL 1 standard laminate | — | — |
| Environ. | Ionic Cleanliness | ≤ 1.56 µg NaCl/cm² (IPC-TM-650 2.3.25) | — | — |
| Environ. | RoHS / REACH / Halogen-Free | Compliant — lead-free processes available | — | — |
IPC-6012 Class 2 defines the acceptance criteria most commercial PCB orders are built to. Here is how our tightest production capability compares on the parameters that matter most for advanced designs.
| Parameter | IPC-6012 Class 2 Baseline | Our Capability |
|---|---|---|
| Max. Layer Count | No maximum defined by standard | 44 layers PROVEN |
| Min. Trace / Space | Defined by design; typical 5/5 mil acceptance | 2 / 2 mil (high-precision tier) 2.5x TIGHTER |
| Hole Position Tolerance | ±0.08 mm (IPC-2221 typical) | ±0.025 mm 3x TIGHTER |
| Min. Annular Ring | 0.05 mm (Class 2 minimum) | 0.10 mm (production standard) RELIABLE |
| Impedance Tolerance | ±10% (typical industry) | ±3% TDR-verified 3x TIGHTER |
| Soldermask Opening | ≥ 3 mil (typical process) | ≥ 1 mil 3x FINER |
| Blind & Buried Vias | Not required by standard | Fully supported, any-layer HDI FULL HDI |
| Aspect Ratio | 8 : 1 (typical commercial) | 12 : 1 50% HIGHER |
| Board Thickness Range | 0.5 – 3.2 mm (typical offering) | 0.2 – 6.4 mm WIDER RANGE |
| Acceptance Standard | IPC-6012 Class 2 | IPC-6012 Class 2 & Class 3 MIL-GRADE |
The capabilities on this page reflect where the industry is heading — not just where it has been.
Device miniaturization in mobile, wearable and medical electronics is driving rapid growth in HDI board demand, with stacked microvia and any-layer architectures becoming standard in flagship designs.
5G infrastructure, EV power electronics and AI edge-compute hardware are pushing average layer counts higher across telecom, automotive and server applications. Builds above 20 layers are increasingly routine.
As data rates climb past 25 Gbps per lane, designers are moving from standard FR-4 to low-Dk/low-Df laminates and Rogers hybrids to control insertion loss and maintain signal fidelity at mmWave frequencies.
Regulatory pressure and OEM sustainability commitments are accelerating the transition to halogen-free laminates and lead-free surface finishes across all market segments, not just consumer electronics.
Growing use of blind and buried vias is closely tied to package substrate density — enabling finer BGA escape routing, shorter signal paths and smaller form factors in SiP and multi-die designs.
Aerospace, defense and medical sectors are increasingly mandating IPC-6012 Class 3 acceptance, pushing fabricators to maintain tighter registration, plating uniformity and cleanliness benchmarks as standard practice.
The same fabrication parameter gets progressively tighter as complexity increases. Use this table to gauge where your design sits — and whether it needs an engineering review before quoting.
| Parameter | Standard | Advanced | High-Precision |
|---|---|---|---|
| Layer Count Range | 1 – 16 layers | 18 – 30 layers | 32 – 44 layers |
| Min. Trace / Space (1 oz) | 4 / 4 mil | 3 / 3 mil | 2 / 2 mil |
| Min. Laser Via Diameter | 0.10 mm | 0.085 mm | 0.075 mm |
| Hole Position Tolerance | ±0.075 mm | ±0.05 mm | ±0.025 mm |
| Impedance Tolerance | ±10% | ±5% | ±3% |
| Soldermask Opening | ≥ 2 mil | ≥ 1.5 mil | ≥ 1 mil |
| Min. PTH Annular Ring | 0.20 mm | 0.15 mm | 0.10 mm |
| Max. Aspect Ratio | 8 : 1 | 10 : 1 | 12 : 1 |
| Track Width Tolerance | ±20% | ±15% | ±10% |
| HDI Build Type | 1+N+1 | 2+N+2 | Any-Layer (i+N+i) |
| Sequential Lamination Cycles | 1 | 2 – 3 | 4+ |
| Warp and Twist | ≤ 0.75% | ≤ 0.50% | ≤ 0.35% |
Six controlled stages, each one holding its own inspection checkpoint before the board moves forward.
Stackup, drill file and tolerance check against this capability sheet before any material is cut.
Photolithographic imaging and etch of inner-layer circuitry to the specified trace and space.
Cores, prepreg and copper foils are aligned and hot-pressed into a single rigid stackup at 375 °F / 275 – 400 psi.
Mechanical and laser drilling, desmear, electroless copper deposition and electrolytic plating of via barrels.
Outer-layer imaging, AOI, soldermask, silkscreen, surface finish application and profile routing.
100% electrical test, final AOI, dimensional check, impedance TDR verification and packaging.
Specifications only matter if they are verified. Every production lot is checked against the tolerances listed above — electrically, dimensionally and, where impedance is controlled, by TDR measurement — with reports supplied as standard.
Still not sure whether your design fits within these ranges? Ask us directly.
We fabricate rigid multilayer PCBs from 1 up to 44 layers. Builds above 20 layers are reviewed by our engineering team at enquiry stage to confirm via strategy, stackup design and lead time — this review is included with every quote, at no extra charge.
Yes. Blind and buried vias are fully supported, including sequential lamination, stacked and staggered microvias, via-in-pad, skip vias and any-layer HDI stackups up to 44 layers. Backdrilling is also available for high-speed designs that need via stub removal.
Standard capability is 4/4 mil (1 oz copper). Advanced is 3/3 mil. High-precision tier reaches 2/2 mil trace and space with tighter track-width tolerance and etch-factor control. Requirements at the high-precision tier go through an engineering review before quoting.
Yes. Standard controlled impedance tolerance is ±10%, with advanced at ±5% and high-precision at ±3%, all TDR-verified and reported with every order, on 4 to 44-layer stackups. Microstrip, stripline, differential pair and coplanar structures are all supported.
HASL (leaded and lead-free), ENIG, ENEPIG, OSP, Immersion Silver, Immersion Tin, selective Hard Gold for edge connectors, and mixed-finish boards (e.g. ENIG + OSP zones). Finish selection is confirmed during DFM review based on your application requirements.
Standard and high-Tg FR-4 (including IT158/IT180A), CEM-3, aluminum and copper-core MCPCB, Rogers and PTFE laminates for RF, Rogers+FR4 hybrids, polyimide for flex-rigid, and halogen-free laminate options. Material selection is part of every DFM review.
Use the Capability Explorer search above to check each critical parameter. If everything falls within Standard or Advanced, you can quote directly. If anything sits in High-Precision, falls outside a listed range, or you are unsure, send us your files for a free DFM review and our engineers will confirm feasibility before you order.
All production is built to IPC-6012 and inspected to IPC-A-600. Standard orders ship at Class 2 acceptance. Class 3 (high-reliability) acceptance is available for aerospace, defense and medical applications — specify at order time.
Send your Gerber and stackup requirements. Our engineers review layer count, materials, trace/space, drilling and impedance targets against this specification sheet within hours.
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